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This is a collection of VLSI/ASIC digital logic design interview questions, partially documented at really taken interviews, partially designed based on the commonly asked questions and usually touched issues. Most of the questions relate to simplified design principles, techniques and tricks, the real-world VLSI/ASIC front-end (logic) design engineers usually use and implement in their work and are aimed to test the ability to solve real world problems considering the quality benchmarks like throughput and latency.

The design concepts used in below questions are:

  • Synchronization

  • Data accumulation (FIFO, read-ahead FIFO, etc)

  • Priority encoding

  • Arbitration (round-robin, weighted round-robin, etc)

  • Data window inspection, shifting, wrapping

  • Data width transitions

  • Data location to time conversion and vice versa

  • Data transmission schemes (credit, etc)

  • Pattern finding

  • Frequency dividing

  • Design for synthesis

  • Etc.

For backend-oriented and more theoretical VLSI/ASIC questions related to digital circuitry theory learned from the academia look in Internet. For other collections of interview questions see Other collections section. Look in Seminal works for best technical papers, which led generations of VLSI engineers in the industry and may be used as a basis for a great portion of interview questions.

Oftentimes the answer to the question is actually an emerging answer, when the initial interviewee solution proposition is followed by interviewer request to further improve the design in order to increase performance, decrease latency or make more efficient use of resources. For answers see Answers section.

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